76 lines
1.8 KiB
Makefile
76 lines
1.8 KiB
Makefile
#
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# OS/161 build environment: compile source files.
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#
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# Usage: use os161.prog.mk or os161.lib.mk
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#
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# Variables controlling this file:
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#
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# SRCS .c and .S files to compile.
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#
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# Provides:
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#
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# OBJS .o files from compilation.
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#
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# Objects list starts empty. It is added to below.
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OBJS=
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clean-local: cleancompile
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cleancompile:
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rm -f $(MYBUILDDIR)/*.[oa]
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distclean-local: distcleancompile
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distcleancompile:
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rm -f $(MYBUILDDIR)/.depend
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#
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# Depend: generate dependency information.
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# Use gcc's -M argument for this.
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#
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# Note that we use -M rather than -MM, to get both system headers
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# and program-local headers. This is because we *are* the system and
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# we might well change those system headers.
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#
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# The fixdepends script transforms the results by substituting some
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# make variables back into them; this way the depend files are
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# independent of (at least some of) the build configuration. It also
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# allows for placing the .o files in the build directory.
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#
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depend-local: $(MYBUILDDIR) .WAIT predepend .WAIT dependcompile
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dependcompile:
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$(CC) $(CFLAGS) $(MORECFLAGS) -M $(SRCS) |\
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$(TOP)/mk/fixdepends.sh '$(INSTALLTOP)' native \
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> $(MYBUILDDIR)/.deptmp
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mv -f $(MYBUILDDIR)/.deptmp $(MYBUILDDIR)/.depend
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.-include "$(MYBUILDDIR)/.depend"
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predepend:
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.PHONY: predepend
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tags: tagscompile
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tagscompile:
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ctags -wtd $(SRCS) *.h
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#
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# Compile rules.
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# We can use the same rules for .c and .S because gcc knows how to handle
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# .S files.
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#
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# Make it so typing "make foo.o" does the right thing.
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#
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.for _S_ in $(SRCS:M*.[cS])
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OBJS+=$(MYBUILDDIR)/$(_S_:T:R).o
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$(MYBUILDDIR)/$(_S_:T:R).o: $(_S_)
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$(CC) $(CFLAGS) $(MORECFLAGS) -c $(_S_) -o $(.TARGET)
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$(_S_:T:R).o: $(MYBUILDDIR)/$(_S_:T:R).o
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.PHONY: $(_S_:T:R).o
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.endfor
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# Make non-file rules PHONY.
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.PHONY: clean-local cleancompile distclean-local distcleancompile
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.PHONY: depend-local dependcompile tags tagscompile
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# End.
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