118 lines
5.2 KiB
C
118 lines
5.2 KiB
C
/*
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* Copyright (c) 2000, 2001, 2002, 2003, 2004, 2005, 2008, 2009
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* The President and Fellows of Harvard College.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE UNIVERSITY AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE UNIVERSITY OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef _MIPS_SPECIALREG_H_
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#define _MIPS_SPECIALREG_H_
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/*
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* Coprocessor 0 (system processor) register numbers
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*/
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#define c0_index $0 /* TLB entry index register */
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#define c0_random $1 /* TLB random slot register */
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#define c0_entrylo $2 /* TLB entry contents (low-order half) */
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/* c0_entrylo0 $2 */ /* MIPS-II and up only */
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/* c0_entrylo1 $3 */ /* MIPS-II and up only */
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#define c0_context $4 /* some precomputed pagetable stuff */
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/* c0_pagemask $5 */ /* MIPS-II and up only */
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/* c0_wired $6 */ /* MIPS-II and up only */
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#define c0_vaddr $8 /* virtual addr of failing memory access */
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#define c0_count $9 /* cycle counter (MIPS-II and up) */
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#define c0_entryhi $10 /* TLB entry contents (high-order half) */
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#define c0_compare $11 /* on-chip timer control (MIPS-II and up) */
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#define c0_status $12 /* processor status register */
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#define c0_cause $13 /* exception cause register */
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#define c0_epc $14 /* exception PC register */
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#define c0_prid $15 /* processor ID register */
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/* c0_config $16 */ /* MIPS-II and up only */
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/* c0_lladdr $17 */ /* MIPS-II and up only */
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/* c0_watchlo $18 */ /* MIPS-II and up only */
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/* c0_watchhi $19 */ /* MIPS-II and up only */
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/*
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* Mode bits in c0_status
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*/
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#define CST_IEc 0x00000001 /* current: interrupt enable */
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#define CST_KUc 0x00000002 /* current: user mode */
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#define CST_IEp 0x00000004 /* previous: interrupt enable */
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#define CST_KUp 0x00000008 /* previous: user mode */
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#define CST_IEo 0x00000010 /* old: interrupt enable */
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#define CST_KUo 0x00000020 /* old: user mode */
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#define CST_MODEMASK 0x0000003f /* mask for the above */
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#define CST_IRQMASK 0x0000ff00 /* mask for the individual irq enable bits */
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#define CST_BEV 0x00400000 /* bootstrap exception vectors flag */
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/*
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* Fields of the c0_cause register
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*/
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#define CCA_UTLB 0x00000001 /* true if UTLB exception (set by our asm) */
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#define CCA_CODE 0x0000003c /* EX_foo in trapframe.h */
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#define CCA_IRQS 0x0000ff00 /* Currently pending interrupts */
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#define CCA_COPN 0x30000000 /* Coprocessor number for EX_CPU */
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#define CCA_JD 0x80000000 /* True if exception happened in jump delay */
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#define CCA_CODESHIFT 2 /* shift for CCA_CODE field */
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/*
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* Fields of the c0_index register
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*/
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#define CIN_P 0x80000000 /* nonzero -> TLB probe found nothing */
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#define CIN_INDEX 0x00003f00 /* 6-bit index into TLB */
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#define CIN_INDEXSHIFT 8 /* shift for CIN_INDEX field */
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/*
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* Fields of the c0_context register
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*
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* The intent of c0_context is that you can manage virtually-mapped
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* page tables in kseg2; then you load the base address of the current
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* page table into c0_context. On a TLB miss the failing address is
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* masked and shifted and appears in the VSHIFT field, and c0_context
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* thereby contains the address of the page table entry you need to
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* load into the TLB. This can be used to make TLB refill very fast.
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*
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* However, in OS/161 we use CTX_PTBASE to hold the current CPU
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* number. This (or something like it) is fairly important to have and
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* there's no other good place in the chip to put it. See discussions
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* elsewhere.
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*/
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#define CTX_VSHIFT 0x001ffffc /* shifted/masked copy of c0_vaddr */
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#define CTX_PTBASE 0xffe00000 /* page table base address */
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#define CTX_PTBASESHIFT 21 /* shift for CTX_PBASE field */
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/*
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* Hardwired exception handler addresses.
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*/
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#define EXADDR_UTLB 0x80000000
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#define EXADDR_GENERAL 0x80000080
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#endif /* _MIPS_SPECIALREG_H_ */
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