345 lines
8.0 KiB
C
345 lines
8.0 KiB
C
/*
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* Copyright (c) 2000, 2001, 2002, 2003, 2004, 2005, 2008, 2009
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* The President and Fellows of Harvard College.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE UNIVERSITY AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE UNIVERSITY OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <types.h>
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#include <kern/unistd.h>
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#include <lib.h>
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#include <mips/specialreg.h>
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#include <mips/trapframe.h>
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#include <cpu.h>
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#include <spl.h>
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#include <clock.h>
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#include <thread.h>
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#include <current.h>
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#include <membar.h>
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#include <synch.h>
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#include <mainbus.h>
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#include <sys161/bus.h>
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#include <lamebus/lamebus.h>
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#include <lamebus/ltrace.h>
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#include "autoconf.h"
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/*
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* CPU frequency used by the on-chip timer.
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*
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* Note that we really ought to measure the CPU frequency against the
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* real-time clock instead of compiling it in like this.
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*/
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#define CPU_FREQUENCY 25000000 /* 25 MHz */
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/*
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* Access to the on-chip timer.
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*
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* The c0_count register increments on every cycle; when the value
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* matches the c0_compare register, the timer interrupt line is
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* asserted. Writing to c0_compare again clears the interrupt.
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*/
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static
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void
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mips_timer_set(uint32_t count)
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{
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/*
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* $11 == c0_compare; we can't use the symbolic name inside
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* the asm string.
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*/
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__asm volatile(
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".set push;" /* save assembler mode */
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".set mips32;" /* allow MIPS32 registers */
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"mtc0 %0, $11;" /* do it */
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".set pop" /* restore assembler mode */
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:: "r" (count));
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}
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/*
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* LAMEbus data for the system. (We have only one LAMEbus per system.)
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* This does not need to be locked, because it's constant once
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* initialized, and initialized before we start other threads or CPUs.
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*/
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static struct lamebus_softc *lamebus;
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void
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mainbus_bootstrap(void)
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{
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/* Interrupts should be off (and have been off since startup) */
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KASSERT(curthread->t_curspl > 0);
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/* Initialize the system LAMEbus data */
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lamebus = lamebus_init();
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/* Probe CPUs (should these be done as device attachments instead?) */
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lamebus_find_cpus(lamebus);
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/*
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* Print the device name for the main bus.
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*/
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kprintf("lamebus0 (system main bus)\n");
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/*
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* Now we can take interrupts without croaking, so turn them on.
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* Some device probes might require being able to get interrupts.
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*/
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spl0();
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/*
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* Now probe all the devices attached to the bus.
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* (This amounts to all devices.)
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*/
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autoconf_lamebus(lamebus, 0);
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/*
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* Configure the MIPS on-chip timer to interrupt HZ times a second.
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*/
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mips_timer_set(CPU_FREQUENCY / HZ);
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}
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/*
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* Start all secondary CPUs.
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*/
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void
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mainbus_start_cpus(void)
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{
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lamebus_start_cpus(lamebus);
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}
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/*
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* Function to generate the memory address (in the uncached segment)
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* for the specified offset into the specified slot's region of the
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* LAMEbus.
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*/
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void *
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lamebus_map_area(struct lamebus_softc *bus, int slot, uint32_t offset)
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{
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uint32_t address;
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(void)bus; // not needed
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KASSERT(slot >= 0 && slot < LB_NSLOTS);
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address = LB_BASEADDR + slot*LB_SLOT_SIZE + offset;
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return (void *)address;
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}
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/*
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* Read a 32-bit register from a LAMEbus device.
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*/
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uint32_t
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lamebus_read_register(struct lamebus_softc *bus, int slot, uint32_t offset)
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{
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uint32_t *ptr;
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ptr = lamebus_map_area(bus, slot, offset);
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/*
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* Make sure the load happens after anything the device has
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* been doing.
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*/
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membar_load_load();
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return *ptr;
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}
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/*
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* Write a 32-bit register of a LAMEbus device.
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*/
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void
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lamebus_write_register(struct lamebus_softc *bus, int slot,
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uint32_t offset, uint32_t val)
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{
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uint32_t *ptr;
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ptr = lamebus_map_area(bus, slot, offset);
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*ptr = val;
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/*
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* Make sure the store happens before we do anything else to
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* the device.
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*/
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membar_store_store();
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}
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/*
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* Power off the system.
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*/
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void
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mainbus_poweroff(void)
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{
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/*
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*
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* Note that lamebus_write_register() doesn't actually access
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* the bus argument, so this will still work if we get here
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* before the bus is initialized.
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*/
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lamebus_poweroff(lamebus);
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}
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/*
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* Reboot the system.
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*/
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void
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mainbus_reboot(void)
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{
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/*
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* The MIPS doesn't appear to have any on-chip reset.
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* LAMEbus doesn't have a reset control, so we just
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* power off instead of rebooting. This would not be
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* so great in a real system, but it's fine for what
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* we're doing.
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*/
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kprintf("Cannot reboot - powering off instead, sorry.\n");
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mainbus_poweroff();
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}
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/*
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* Halt the system.
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* On some systems, this would return to the boot monitor. But we don't
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* have one.
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*/
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void
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mainbus_halt(void)
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{
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cpu_halt();
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}
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/*
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* Called to reset the system from panic().
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*
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* By the time we get here, the system may well be sufficiently hosed
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* as to panic recursively if we do much of anything. So just power off.
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* (We'd reboot, but System/161 doesn't do that.)
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*/
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void
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mainbus_panic(void)
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{
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mainbus_poweroff();
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}
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/*
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* Function to get the size of installed physical RAM from the LAMEbus
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* controller.
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*/
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uint32_t
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mainbus_ramsize(void)
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{
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uint32_t ramsize;
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ramsize = lamebus_ramsize();
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/*
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* This is the same as the last physical address, as long as
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* we have less than 508 megabytes of memory. The LAMEbus I/O
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* area occupies the space between 508 megabytes and 512
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* megabytes, so if we had more RAM than this it would have to
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* be discontiguous. This is not a case we are going to worry
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* about.
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*/
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if (ramsize > 508*1024*1024) {
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ramsize = 508*1024*1024;
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}
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return ramsize;
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}
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/*
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* Send IPI.
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*/
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void
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mainbus_send_ipi(struct cpu *target)
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{
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lamebus_assert_ipi(lamebus, target);
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}
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/*
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* Trigger the debugger.
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*/
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void
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mainbus_debugger(void)
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{
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ltrace_stop(0);
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}
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/*
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* Interrupt dispatcher.
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*/
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/* Wiring of LAMEbus interrupts to bits in the cause register */
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#define LAMEBUS_IRQ_BIT 0x00000400 /* all system bus slots */
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#define LAMEBUS_IPI_BIT 0x00000800 /* inter-processor interrupt */
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#define MIPS_TIMER_BIT 0x00008000 /* on-chip timer */
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void
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mainbus_interrupt(struct trapframe *tf)
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{
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uint32_t cause;
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bool seen = false;
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/* interrupts should be off */
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KASSERT(curthread->t_curspl > 0);
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cause = tf->tf_cause;
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if (cause & LAMEBUS_IRQ_BIT) {
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lamebus_interrupt(lamebus);
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seen = true;
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}
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if (cause & LAMEBUS_IPI_BIT) {
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interprocessor_interrupt();
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lamebus_clear_ipi(lamebus, curcpu);
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seen = true;
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}
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if (cause & MIPS_TIMER_BIT) {
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/* Reset the timer (this clears the interrupt) */
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mips_timer_set(CPU_FREQUENCY / HZ);
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/* and call hardclock */
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hardclock();
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seen = true;
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}
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if (!seen) {
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if ((cause & CCA_IRQS) == 0) {
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/*
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* Don't panic here; this can happen if an
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* interrupt line asserts (very) briefly and
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* turns off again before we get as far as
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* reading the cause register. This was
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* actually seen... once.
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*/
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}
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else {
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/*
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* But if we get an interrupt on an interrupt
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* line that's not supposed to be wired up,
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* complain.
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*/
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panic("Unknown interrupt; cause register is %08x\n",
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cause);
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}
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}
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}
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