205 lines
7.1 KiB
ArmAsm
205 lines
7.1 KiB
ArmAsm
/*
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* Copyright (c) 2000, 2001, 2002, 2003, 2004, 2005, 2008, 2009
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* The President and Fellows of Harvard College.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE UNIVERSITY AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE UNIVERSITY OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <kern/mips/regdefs.h>
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#include <mips/specialreg.h>
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/*
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* TLB handling for the MIPS-161.
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*
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* The MIPS-161 uses the simpler MIPS-1 (r2000/r3000) TLB rather
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* than the paired-page TLB of later MIPS models.
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*
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* However, we handle MIPS32 pipeline hazards. If you want to run on
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* a real MIPS-1, change the ssnops to plain nops and check where and
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* how many you need in the matching processor docs.
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*
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* (ssnop means "superscalar nop"; it exists because the pipeline
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* hazards require a fixed number of cycles, and a superscalar CPU can
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* potentially issue arbitrarily many nops in one cycle.)
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*/
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.text
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.set noreorder
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.set mips32 /* so we can use ssnop */
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/*
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* tlb_random: use the "tlbwr" instruction to write a TLB entry
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* into a (very pseudo-) random slot in the TLB.
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*
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* Pipeline hazard: must wait between setting entryhi/lo and
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* doing the tlbwr. Use two cycles; some processors may vary.
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*/
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.globl tlb_random
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.type tlb_random,@function
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.ent tlb_random
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tlb_random:
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mtc0 a0, c0_entryhi /* store the passed entry into the */
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mtc0 a1, c0_entrylo /* tlb entry registers */
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ssnop /* wait for pipeline hazard */
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ssnop
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tlbwr /* do it */
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j ra
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nop
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.end tlb_random
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/*
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* tlb_write: use the "tlbwi" instruction to write a TLB entry
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* into a selected slot in the TLB.
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*
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* Pipeline hazard: must wait between setting entryhi/lo and
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* doing the tlbwi. Use two cycles; some processors may vary.
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*/
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.text
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.globl tlb_write
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.type tlb_write,@function
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.ent tlb_write
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tlb_write:
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mtc0 a0, c0_entryhi /* store the passed entry into the */
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mtc0 a1, c0_entrylo /* tlb entry registers */
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sll t0, a2, CIN_INDEXSHIFT /* shift the passed index into place */
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mtc0 t0, c0_index /* store the shifted index into the index register */
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ssnop /* wait for pipeline hazard */
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ssnop
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tlbwi /* do it */
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j ra
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nop
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.end tlb_write
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/*
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* tlb_read: use the "tlbr" instruction to read a TLB entry
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* from a selected slot in the TLB.
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*
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* Pipeline hazard: must wait between setting c0_index and
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* doing the tlbr. Use two cycles; some processors may vary.
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* Similarly, three more cycles before reading c0_entryhi/lo.
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*/
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.text
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.globl tlb_read
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.type tlb_read,@function
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.ent tlb_read
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tlb_read:
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sll t0, a2, CIN_INDEXSHIFT /* shift the passed index into place */
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mtc0 t0, c0_index /* store the shifted index into the index register */
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ssnop /* wait for pipeline hazard */
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ssnop
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tlbr /* do it */
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ssnop /* wait for pipeline hazard */
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ssnop
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ssnop
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mfc0 t0, c0_entryhi /* get the tlb entry out of the */
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mfc0 t1, c0_entrylo /* tlb entry registers */
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sw t0, 0(a0) /* store through the passed pointer */
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j ra
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sw t1, 0(a1) /* store (in delay slot) */
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.end tlb_read
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/*
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* tlb_probe: use the "tlbp" instruction to find the index in the
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* TLB of a TLB entry matching the relevant parts of the one supplied.
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*
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* Pipeline hazard: must wait between setting c0_entryhi/lo and
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* doing the tlbp. Use two cycles; some processors may vary.
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* Similarly, two more cycles before reading c0_index.
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*/
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.text
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.globl tlb_probe
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.type tlb_probe,@function
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.ent tlb_probe
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tlb_probe:
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mtc0 a0, c0_entryhi /* store the passed entry into the */
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mtc0 a1, c0_entrylo /* tlb entry registers */
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ssnop /* wait for pipeline hazard */
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ssnop
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tlbp /* do it */
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ssnop /* wait for pipeline hazard */
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ssnop
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mfc0 t0, c0_index /* fetch the index back in t0 */
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/*
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* If the high bit (CIN_P) of c0_index is set, the probe failed.
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* The high bit is not set <--> c0_index (now in t0) >= 0.
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*/
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bgez t0, 1f /* did probe succeed? if so, skip forward */
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nop /* delay slot */
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addi v0, z0, -1 /* set return value to -1 to indicate failure */
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j ra /* done */
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nop /* delay slot */
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1:
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/* succeeded - get the index field from the index register value */
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andi t1, t0, CIN_INDEX /* mask off the field */
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j ra /* done */
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sra v0, t1, CIN_INDEXSHIFT /* shift it (in delay slot) */
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.end tlb_probe
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/*
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* tlb_reset
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*
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* Initialize the TLB. At processor startup, the TLB state is completely
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* undefined. So be sure to avoid creating any duplicates. Also make sure
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* that the initialization entries don't duplicate the INVALID entries
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* defined in tlb.h. (This way you can write the invalid entries in
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* without having to use tlbp to find out if they're going to cause dups.)
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*
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* This function is not defined in tlb.h because it's only called from
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* start.S.
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*
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* Pipeline hazards are as above.
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*/
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.text
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.globl tlb_reset
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.type tlb_reset,@function
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.ent tlb_reset
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tlb_reset:
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li t0, 0 /* t0 <- tlb index number (shifted) */
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li t1, 0x81000000 /* t1 <- tlb reset vaddr */
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1:
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mtc0 $0, c0_entrylo /* set up proposed tlb entry for reset */
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mtc0 t1, c0_entryhi
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ssnop /* wait for pipeline hazard */
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ssnop
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tlbp /* check if it already exists */
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ssnop /* wait for pipeline hazard */
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ssnop
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mfc0 t2, c0_index
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bgez t2, 1b /* if it does, loop back */
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addiu t1, t1, 0x1000 /* next vaddr (in delay slot) */
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mtc0 t0, c0_index /* doesn't exist, set index to write to */
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ssnop /* wait for pipeline hazard */
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ssnop
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addiu t0, t0, 0x100 /* next tlb index (shifted) */
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bne t0, 0x4000, 1b /* if it's not the last tlb index, loop */
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tlbwi /* write tlb entry (in delay slot) */
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j ra /* done */
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nop /* delay slot */
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.end tlb_reset
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