356 lines
11 KiB
ArmAsm
356 lines
11 KiB
ArmAsm
/*
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* Copyright (c) 2000, 2001, 2002, 2003, 2004, 2005, 2008, 2009
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* The President and Fellows of Harvard College.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE UNIVERSITY AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE UNIVERSITY OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <kern/mips/regdefs.h>
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#include <mips/specialreg.h>
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/*
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* Entry points for exceptions.
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*
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* MIPS-1 (r2000/r3000) style exception handling, with the "rfe"
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* instruction rather than "eret", and the three sets of status bits.
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*/
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/*
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* Do not allow the assembler to use $1 (at), because we need to be
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* able to save it.
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*/
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.set noat
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.set noreorder
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/*
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* UTLB exception handler.
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*
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* This code is copied to address 0x80000000, where the MIPS processor
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* automatically invokes it.
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*
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* To avoid colliding with the other exception code, it must not
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* exceed 128 bytes (32 instructions).
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*
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* This is the special entry point for the fast-path TLB refill for
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* faults in the user address space. We don't implement fast-path TLB
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* refill by default. Note that if you do, you either need to make
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* sure the refill code doesn't fault or write extra code in
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* common_exception to tidy up after such faults.
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*/
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.text
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.globl mips_utlb_handler
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.type mips_utlb_handler,@function
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.ent mips_utlb_handler
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mips_utlb_handler:
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j common_exception /* Don't need to do anything special */
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nop /* Delay slot */
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.globl mips_utlb_end
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mips_utlb_end:
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.end mips_utlb_handler
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/*
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* General exception handler.
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*
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* This code is copied to address 0x80000080, where
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* the MIPS processor automatically invokes it.
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*/
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.text
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.globl mips_general_handler
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.type mips_general_handler,@function
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.ent mips_general_handler
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mips_general_handler:
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j common_exception /* Don't need to do anything special */
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nop /* Delay slot */
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.globl mips_general_end
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mips_general_end:
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.end mips_general_handler
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/* This keeps gdb from conflating common_exception and mips_general_end */
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nop /* padding */
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/*
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* Shared exception code for both handlers.
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*/
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.text
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.type common_exception,@function
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.ent common_exception
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common_exception:
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mfc0 k0, c0_status /* Get status register */
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andi k0, k0, CST_KUp /* Check the we-were-in-user-mode bit */
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beq k0, $0, 1f /* If clear, from kernel, already have stack */
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nop /* delay slot */
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/* Coming from user mode - find kernel stack */
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mfc0 k1, c0_context /* we keep the CPU number here */
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srl k1, k1, CTX_PTBASESHIFT /* shift it to get just the CPU number */
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sll k1, k1, 2 /* shift it back to make an array index */
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lui k0, %hi(cpustacks) /* get base address of cpustacks[] */
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addu k0, k0, k1 /* index it */
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move k1, sp /* Save previous stack pointer in k1 */
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b 2f /* Skip to common code */
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lw sp, %lo(cpustacks)(k0) /* Load kernel stack pointer (in delay slot) */
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1:
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/* Coming from kernel mode - just save previous stuff */
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move k1, sp /* Save previous stack in k1 (delay slot) */
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2:
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/*
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* At this point:
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* Interrupts are off. (The processor did this for us.)
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* k0 contains the value for curthread, to go into s7.
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* k1 contains the old stack pointer.
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* sp points into the kernel stack.
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* All other registers are untouched.
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*/
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/*
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* Allocate stack space for 37 words to hold the trap frame,
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* plus four more words for a minimal argument block, plus
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* one more for proper (64-bit) stack alignment.
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*/
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addi sp, sp, -168
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/*
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* Save general registers.
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* We exclude k0/k1, which the kernel is free to clobber (and which
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* we already have clobbered), and $0, whose value is fixed.
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*
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* The order here must match mips/include/trapframe.h.
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*
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* gdb disassembles this code to try to figure out what registers
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* are where, and it isn't very bright. So in order to make gdb be
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* able to trace the stack back through here, we play some silly
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* games.
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*
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* In particular:
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* (1) We store the return address register into the epc slot,
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* which makes gdb think it's the return address slot. Then
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* we store the real epc value over that.
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* (2) We store the current sp into the sp slot, which makes gdb
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* think it's the stack pointer slot. Then we store the real
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* value.
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* (3) gdb also assumes that saved registers in a function are
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* saved in order. This is why we put epc where it is, and
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* handle the real value of ra afterwards.
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* (4) Because gdb will think we're saving k0 and k1, we need to
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* leave slots for them in the trap frame, even though the
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* stuff we save there is useless.
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*
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* This logic has not been tested against a recent gdb and has
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* probably bitrotted. Someone(TM) should figure out what gdb
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* currently expects -- or maybe even patch gdb to understand a
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* better form of this that doesn't waste so many cycles.
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*/
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sw ra, 160(sp) /* dummy for gdb */
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sw s8, 156(sp) /* save s8 */
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sw sp, 152(sp) /* dummy for gdb */
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sw gp, 148(sp) /* save gp */
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sw k1, 144(sp) /* dummy for gdb */
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sw k0, 140(sp) /* dummy for gdb */
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sw k1, 152(sp) /* real saved sp */
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nop /* delay slot for store */
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mfc0 k1, c0_epc /* Copr.0 reg 13 == PC for exception */
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sw k1, 160(sp) /* real saved PC */
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sw t9, 136(sp)
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sw t8, 132(sp)
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sw s7, 128(sp)
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sw s6, 124(sp)
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sw s5, 120(sp)
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sw s4, 116(sp)
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sw s3, 112(sp)
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sw s2, 108(sp)
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sw s1, 104(sp)
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sw s0, 100(sp)
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sw t7, 96(sp)
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sw t6, 92(sp)
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sw t5, 88(sp)
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sw t4, 84(sp)
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sw t3, 80(sp)
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sw t2, 76(sp)
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sw t1, 72(sp)
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sw t0, 68(sp)
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sw a3, 64(sp)
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sw a2, 60(sp)
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sw a1, 56(sp)
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sw a0, 52(sp)
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sw v1, 48(sp)
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sw v0, 44(sp)
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sw AT, 40(sp)
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sw ra, 36(sp)
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/*
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* Save special registers.
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*/
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mfhi t0
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mflo t1
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sw t0, 32(sp)
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sw t1, 28(sp)
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/*
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* Save remaining exception context information.
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*/
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mfc0 t2, c0_status /* Copr.0 reg 11 == status */
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sw t2, 20(sp)
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mfc0 t3, c0_vaddr /* Copr.0 reg 8 == faulting vaddr */
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sw t3, 16(sp)
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mfc0 t4, c0_cause
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sw t4, 24(sp) /* Copr.0 reg 13 == exception cause */
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/*
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* Pretend to save $0 for gdb's benefit.
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*/
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sw $0, 12(sp)
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/*
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* Load the curthread register if coming from user mode.
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*/
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andi k0, t2, CST_KUp /* Check the we-were-in-user-mode bit */
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beq k0, $0, 3f /* If clear, were in kernel, skip ahead */
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nop /* delay slot */
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mfc0 k1, c0_context /* we keep the CPU number here */
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srl k1, k1, CTX_PTBASESHIFT /* shift it to get just the CPU number */
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sll k1, k1, 2 /* shift it back to make an array index */
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lui k0, %hi(cputhreads) /* get base address of cputhreads[] */
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addu k0, k0, k1 /* index it */
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lw s7, %lo(cputhreads)(k0) /* Load curthread value */
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3:
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/*
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* Load the kernel GP value.
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*/
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la gp, _gp
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/*
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* Prepare to call mips_trap(struct trapframe *)
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*/
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addiu a0, sp, 16 /* set argument - pointer to the trapframe */
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jal mips_trap /* call it */
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nop /* delay slot */
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/* Something must be here or gdb doesn't find the stack frame. */
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nop
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/*
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* Now restore stuff and return from the exception.
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* Interrupts should be off.
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*/
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exception_return:
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/* 16(sp) no need to restore tf_vaddr */
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lw t0, 20(sp) /* load status register value into t0 */
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nop /* load delay slot */
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mtc0 t0, c0_status /* store it back to coprocessor 0 */
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/* 24(sp) no need to restore tf_cause */
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/* restore special registers */
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lw t1, 28(sp)
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lw t0, 32(sp)
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mtlo t1
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mthi t0
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/* load the general registers */
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lw ra, 36(sp)
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lw AT, 40(sp)
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lw v0, 44(sp)
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lw v1, 48(sp)
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lw a0, 52(sp)
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lw a1, 56(sp)
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lw a2, 60(sp)
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lw a3, 64(sp)
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lw t0, 68(sp)
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lw t1, 72(sp)
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lw t2, 76(sp)
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lw t3, 80(sp)
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lw t4, 84(sp)
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lw t5, 88(sp)
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lw t6, 92(sp)
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lw t7, 96(sp)
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lw s0, 100(sp)
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lw s1, 104(sp)
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lw s2, 108(sp)
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lw s3, 112(sp)
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lw s4, 116(sp)
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lw s5, 120(sp)
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lw s6, 124(sp)
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lw s7, 128(sp)
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lw t8, 132(sp)
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lw t9, 136(sp)
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/* 140(sp) "saved" k0 was dummy garbage anyway */
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/* 144(sp) "saved" k1 was dummy garbage anyway */
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lw gp, 148(sp) /* restore gp */
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/* 152(sp) stack pointer - below */
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lw s8, 156(sp) /* restore s8 */
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lw k0, 160(sp) /* fetch exception return PC into k0 */
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lw sp, 152(sp) /* fetch saved sp (must be last) */
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/* done */
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jr k0 /* jump back */
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rfe /* in delay slot */
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.end common_exception
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/*
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* Code to enter user mode for the first time.
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* Does not return.
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*
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* This is called from mips_usermode().
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* Interrupts on this processor should be off.
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*/
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.text
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.globl asm_usermode
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.type asm_usermode,@function
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.ent asm_usermode
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asm_usermode:
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/*
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* a0 is the address of a trapframe to use for exception "return".
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* It's allocated on our stack.
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*
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* Move it to the stack pointer - we don't need the actual stack
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* position any more. (When we come back from usermode, cpustacks[]
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* will be used to reinitialize our stack pointer, and that was
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* set by mips_usermode.)
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*
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* Then just jump to the exception return code above.
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*/
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j exception_return
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addiu sp, a0, -16 /* in delay slot */
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.end asm_usermode
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