94 lines
4.1 KiB
C
94 lines
4.1 KiB
C
/*
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* Copyright (c) 2013
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* The President and Fellows of Harvard College.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE UNIVERSITY AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE UNIVERSITY OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef _MEMBAR_H_
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#define _MEMBAR_H_
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/*
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* Memory barriers. These create ordering barriers in CPU memory
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* accesses as actually issued by the CPU to the cache and memory
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* system. Because superscalar CPUs can execute many instructions at
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* once, they can potentially be retired in a different order from
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* what's written in your code. Normally this doesn't matter, but
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* sometimes it does (e.g. when writing to device registers) and in
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* those cases you need to insert memory barrier instructions to
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* create ordering guarantees.
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*
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* membar_load_load creates an ordering barrier between preceding
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* loads (from memory to registers) and subsequent loads, but has
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* (potentially) no effect on stores. This is what some people call a
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* "load fence".
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*
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* membar_store_store creates an ordering barrier between preceding
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* stores (from registers to memory) and subsequent stores, but has
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* (potentially) no effect on loads. This is what some people call a
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* "store" or "write fence".
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*
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* membar_store_any creates an ordering barrier between preceding
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* stores and subsequent stores *and* loads. Preceding loads may be
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* delayed past the barrier. This is the behavior needed for
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* operations comparable to spinlock_acquire().
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*
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* membar_any_store creates an ordering barrier between preceding
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* loads and stores and subsequent stores. Following loads may be
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* executed before the barrier. This is the behavior needed for
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* operations comparable to spinlock_release().
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*
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* membar_any_any creates a full ordering barrier, between preceding
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* loads and stores and following loads and stores.
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*
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* In OS/161 we assume that the spinlock operations include any memory
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* barrier instructions they require. (On many CPUs the synchronized/
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* locked instructions used to implement spinlocks are themselves
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* implicit memory barriers.) You do not need to use membar_store_any
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* and membar_any_store unless rolling your own lock-like objects,
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* using atomic operations, implementing lock-free data structures, or
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* talking to hardware devices.
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*
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* There is a lot of FUD about memory barriers circulating on the
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* internet. Please ask your course staff if you have questions or
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* concerns.
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*/
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/* Inlining support - for making sure an out-of-line copy gets built */
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#ifndef MEMBAR_INLINE
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#define MEMBAR_INLINE INLINE
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#endif
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MEMBAR_INLINE void membar_load_load(void);
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MEMBAR_INLINE void membar_store_store(void);
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MEMBAR_INLINE void membar_store_any(void);
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MEMBAR_INLINE void membar_any_store(void);
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MEMBAR_INLINE void membar_any_any(void);
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/* Get the implementation. */
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#include <machine/membar.h>
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#endif /* _MEMBAR_H_ */
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