Initial Spring 2016 commit.
This commit is contained in:
Geoffrey Challen
665
kern/dev/lamebus/lamebus.c
Normal file
665
kern/dev/lamebus/lamebus.c
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@@ -0,0 +1,665 @@
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/*
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* Copyright (c) 2000, 2001, 2002, 2003, 2004, 2005, 2008, 2009
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* The President and Fellows of Harvard College.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE UNIVERSITY AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE UNIVERSITY OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* Machine-independent LAMEbus code.
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*/
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#include <types.h>
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#include <lib.h>
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#include <cpu.h>
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#include <membar.h>
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#include <spinlock.h>
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#include <current.h>
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#include <lamebus/lamebus.h>
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/* Register offsets within each config region */
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#define CFGREG_VID 0 /* Vendor ID */
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#define CFGREG_DID 4 /* Device ID */
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#define CFGREG_DRL 8 /* Device Revision Level */
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/* LAMEbus controller private registers (offsets within its config region) */
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#define CTLREG_RAMSZ 0x200
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#define CTLREG_IRQS 0x204
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#define CTLREG_PWR 0x208
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#define CTLREG_IRQE 0x20c
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#define CTLREG_CPUS 0x210
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#define CTLREG_CPUE 0x214
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#define CTLREG_SELF 0x218
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/* LAMEbus CPU control registers (offsets within each per-cpu region) */
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#define CTLCPU_CIRQE 0x000
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#define CTLCPU_CIPI 0x004
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#define CTLCPU_CRAM 0x300
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/*
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* Read a config register for the given slot.
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*/
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static
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inline
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uint32_t
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read_cfg_register(struct lamebus_softc *lb, int slot, uint32_t offset)
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{
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/* Note that lb might be NULL on some platforms in some contexts. */
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offset += LB_CONFIG_SIZE*slot;
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return lamebus_read_register(lb, LB_CONTROLLER_SLOT, offset);
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}
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/*
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* Write a config register for a given slot.
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*/
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static
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inline
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void
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write_cfg_register(struct lamebus_softc *lb, int slot, uint32_t offset,
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uint32_t val)
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{
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offset += LB_CONFIG_SIZE*slot;
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lamebus_write_register(lb, LB_CONTROLLER_SLOT, offset, val);
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}
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/*
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* Read one of the bus controller's registers.
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*/
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static
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inline
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uint32_t
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read_ctl_register(struct lamebus_softc *lb, uint32_t offset)
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{
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/* Note that lb might be NULL on some platforms in some contexts. */
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return read_cfg_register(lb, LB_CONTROLLER_SLOT, offset);
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}
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/*
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* Write one of the bus controller's registers.
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*/
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static
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inline
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void
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write_ctl_register(struct lamebus_softc *lb, uint32_t offset, uint32_t val)
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{
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write_cfg_register(lb, LB_CONTROLLER_SLOT, offset, val);
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}
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/*
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* Write one of the bus controller's CPU control registers.
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*/
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static
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inline
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void
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write_ctlcpu_register(struct lamebus_softc *lb, unsigned hw_cpunum,
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uint32_t offset, uint32_t val)
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{
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offset += LB_CTLCPU_OFFSET + hw_cpunum * LB_CTLCPU_SIZE;
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lamebus_write_register(lb, LB_CONTROLLER_SLOT, offset, val);
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}
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/*
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* Find and create secondary CPUs.
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*/
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void
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lamebus_find_cpus(struct lamebus_softc *lamebus)
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{
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uint32_t mainboard_vid, mainboard_did;
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uint32_t cpumask, self, bit, val;
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unsigned i, numcpus, bootcpu;
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unsigned hwnum[32];
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mainboard_vid = read_cfg_register(lamebus, LB_CONTROLLER_SLOT,
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CFGREG_VID);
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mainboard_did = read_cfg_register(lamebus, LB_CONTROLLER_SLOT,
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CFGREG_DID);
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if (mainboard_vid == LB_VENDOR_CS161 &&
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mainboard_did == LBCS161_UPBUSCTL) {
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/* Old uniprocessor mainboard; no cpu registers. */
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lamebus->ls_uniprocessor = 1;
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return;
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}
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cpumask = read_ctl_register(lamebus, CTLREG_CPUS);
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self = read_ctl_register(lamebus, CTLREG_SELF);
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numcpus = 0;
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bootcpu = 0;
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for (i=0; i<32; i++) {
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bit = (uint32_t)1 << i;
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if ((cpumask & bit) != 0) {
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if (self & bit) {
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bootcpu = numcpus;
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curcpu->c_hardware_number = i;
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}
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hwnum[numcpus] = i;
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numcpus++;
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}
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}
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for (i=0; i<numcpus; i++) {
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if (i != bootcpu) {
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cpu_create(hwnum[i]);
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}
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}
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/*
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* By default, route all interrupts only to the boot cpu. We
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* could be arbitrarily more elaborate, up to things like
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* dynamic load balancing.
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*/
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for (i=0; i<numcpus; i++) {
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if (i != bootcpu) {
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val = 0;
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}
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else {
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val = 0xffffffff;
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}
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write_ctlcpu_register(lamebus, hwnum[i], CTLCPU_CIRQE, val);
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}
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}
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/*
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* Start up secondary CPUs.
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*
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* The first word of the CRAM area is set to the entry point for new
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* CPUs; the second to the (software) CPU number. Note that the logic
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* here assumes the boot CPU is CPU 0 and the others are 1-N as
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* created in the function above. This is fine if all CPUs are on
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* LAMEbus; if in some environment there are other CPUs about as well
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* this logic will have to be made more complex.
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*/
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void
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lamebus_start_cpus(struct lamebus_softc *lamebus)
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{
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uint32_t cpumask, self, bit;
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uint32_t ctlcpuoffset;
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uint32_t *cram;
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unsigned i;
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unsigned cpunum;
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if (lamebus->ls_uniprocessor) {
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return;
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}
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cpumask = read_ctl_register(lamebus, CTLREG_CPUS);
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self = read_ctl_register(lamebus, CTLREG_SELF);
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/* Poke in the startup address. */
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cpunum = 1;
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for (i=0; i<32; i++) {
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bit = (uint32_t)1 << i;
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if ((cpumask & bit) != 0) {
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if (self & bit) {
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continue;
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}
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ctlcpuoffset = LB_CTLCPU_OFFSET + i * LB_CTLCPU_SIZE;
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cram = lamebus_map_area(lamebus,
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LB_CONTROLLER_SLOT,
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ctlcpuoffset + CTLCPU_CRAM);
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cram[0] = (uint32_t)cpu_start_secondary;
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cram[1] = cpunum++;
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}
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}
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/* Ensure all the above writes get flushed. */
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membar_store_store();
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/* Now, enable them all. */
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write_ctl_register(lamebus, CTLREG_CPUE, cpumask);
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}
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/*
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* Probe function.
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*
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* Given a LAMEbus, look for a device that's not already been marked
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* in use, has the specified IDs, and has a device revision level at
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* least as high as the minimum specified.
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*
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* Returns the slot number found (0-31) or -1 if nothing suitable was
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* found.
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*
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* If VERSION_RET is not null, return the device version found. This
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* allows drivers to blacklist specific versions or otherwise conduct
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* more specific checks.
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*/
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int
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lamebus_probe(struct lamebus_softc *sc,
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uint32_t vendorid, uint32_t deviceid,
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uint32_t lowver, uint32_t *version_ret)
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{
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int slot;
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uint32_t val;
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/*
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* Because the slot information in sc is used when dispatching
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* interrupts, disable interrupts while working with it.
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*/
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spinlock_acquire(&sc->ls_lock);
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for (slot=0; slot<LB_NSLOTS; slot++) {
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if (sc->ls_slotsinuse & (1<<slot)) {
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/* Slot already in use; skip */
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continue;
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}
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val = read_cfg_register(sc, slot, CFGREG_VID);
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if (val!=vendorid) {
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/* Wrong vendor id */
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continue;
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}
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val = read_cfg_register(sc, slot, CFGREG_DID);
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if (val != deviceid) {
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/* Wrong device id */
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continue;
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}
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val = read_cfg_register(sc, slot, CFGREG_DRL);
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if (val < lowver) {
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/* Unsupported device revision */
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continue;
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}
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if (version_ret != NULL) {
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*version_ret = val;
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}
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/* Found something */
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spinlock_release(&sc->ls_lock);
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return slot;
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}
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/* Found nothing */
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spinlock_release(&sc->ls_lock);
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return -1;
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}
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/*
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* Mark that a slot is in use.
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* This prevents the probe routine from returning the same device over
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* and over again.
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*/
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void
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lamebus_mark(struct lamebus_softc *sc, int slot)
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{
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uint32_t mask = ((uint32_t)1) << slot;
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KASSERT(slot>=0 && slot < LB_NSLOTS);
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spinlock_acquire(&sc->ls_lock);
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if ((sc->ls_slotsinuse & mask)!=0) {
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panic("lamebus_mark: slot %d already in use\n", slot);
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}
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sc->ls_slotsinuse |= mask;
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spinlock_release(&sc->ls_lock);
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}
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/*
|
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* Mark that a slot is no longer in use.
|
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*/
|
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void
|
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lamebus_unmark(struct lamebus_softc *sc, int slot)
|
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{
|
||||
uint32_t mask = ((uint32_t)1) << slot;
|
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KASSERT(slot>=0 && slot < LB_NSLOTS);
|
||||
|
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spinlock_acquire(&sc->ls_lock);
|
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|
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if ((sc->ls_slotsinuse & mask)==0) {
|
||||
panic("lamebus_mark: slot %d not marked in use\n", slot);
|
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}
|
||||
|
||||
sc->ls_slotsinuse &= ~mask;
|
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|
||||
spinlock_release(&sc->ls_lock);
|
||||
}
|
||||
|
||||
/*
|
||||
* Register a function (and a device context pointer) to be called
|
||||
* when a particular slot signals an interrupt.
|
||||
*/
|
||||
void
|
||||
lamebus_attach_interrupt(struct lamebus_softc *sc, int slot,
|
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void *devdata,
|
||||
void (*irqfunc)(void *devdata))
|
||||
{
|
||||
uint32_t mask = ((uint32_t)1) << slot;
|
||||
KASSERT(slot>=0 && slot < LB_NSLOTS);
|
||||
|
||||
spinlock_acquire(&sc->ls_lock);
|
||||
|
||||
if ((sc->ls_slotsinuse & mask)==0) {
|
||||
panic("lamebus_attach_interrupt: slot %d not marked in use\n",
|
||||
slot);
|
||||
}
|
||||
|
||||
KASSERT(sc->ls_devdata[slot]==NULL);
|
||||
KASSERT(sc->ls_irqfuncs[slot]==NULL);
|
||||
|
||||
sc->ls_devdata[slot] = devdata;
|
||||
sc->ls_irqfuncs[slot] = irqfunc;
|
||||
|
||||
spinlock_release(&sc->ls_lock);
|
||||
}
|
||||
|
||||
/*
|
||||
* Unregister a function that was being called when a particular slot
|
||||
* signaled an interrupt.
|
||||
*/
|
||||
void
|
||||
lamebus_detach_interrupt(struct lamebus_softc *sc, int slot)
|
||||
{
|
||||
uint32_t mask = ((uint32_t)1) << slot;
|
||||
KASSERT(slot>=0 && slot < LB_NSLOTS);
|
||||
|
||||
spinlock_acquire(&sc->ls_lock);
|
||||
|
||||
if ((sc->ls_slotsinuse & mask)==0) {
|
||||
panic("lamebus_detach_interrupt: slot %d not marked in use\n",
|
||||
slot);
|
||||
}
|
||||
|
||||
KASSERT(sc->ls_irqfuncs[slot]!=NULL);
|
||||
|
||||
sc->ls_devdata[slot] = NULL;
|
||||
sc->ls_irqfuncs[slot] = NULL;
|
||||
|
||||
spinlock_release(&sc->ls_lock);
|
||||
}
|
||||
|
||||
/*
|
||||
* Mask/unmask an interrupt using the global IRQE register.
|
||||
*/
|
||||
void
|
||||
lamebus_mask_interrupt(struct lamebus_softc *lamebus, int slot)
|
||||
{
|
||||
uint32_t bits, mask = ((uint32_t)1) << slot;
|
||||
KASSERT(slot >= 0 && slot < LB_NSLOTS);
|
||||
|
||||
spinlock_acquire(&lamebus->ls_lock);
|
||||
bits = read_ctl_register(lamebus, CTLREG_IRQE);
|
||||
bits &= ~mask;
|
||||
write_ctl_register(lamebus, CTLREG_IRQE, bits);
|
||||
spinlock_release(&lamebus->ls_lock);
|
||||
}
|
||||
|
||||
void
|
||||
lamebus_unmask_interrupt(struct lamebus_softc *lamebus, int slot)
|
||||
{
|
||||
uint32_t bits, mask = ((uint32_t)1) << slot;
|
||||
KASSERT(slot >= 0 && slot < LB_NSLOTS);
|
||||
|
||||
spinlock_acquire(&lamebus->ls_lock);
|
||||
bits = read_ctl_register(lamebus, CTLREG_IRQE);
|
||||
bits |= mask;
|
||||
write_ctl_register(lamebus, CTLREG_IRQE, bits);
|
||||
spinlock_release(&lamebus->ls_lock);
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* LAMEbus interrupt handling function. (Machine-independent!)
|
||||
*/
|
||||
void
|
||||
lamebus_interrupt(struct lamebus_softc *lamebus)
|
||||
{
|
||||
/*
|
||||
* Note that despite the fact that "spl" stands for "set
|
||||
* priority level", we don't actually support interrupt
|
||||
* priorities. When an interrupt happens, we look through the
|
||||
* slots to find the first interrupting device and call its
|
||||
* interrupt routine, no matter what that device is.
|
||||
*
|
||||
* Note that the entire LAMEbus uses only one on-cpu interrupt line.
|
||||
* Thus, we do not use any on-cpu interrupt priority system either.
|
||||
*/
|
||||
|
||||
int slot;
|
||||
uint32_t mask;
|
||||
uint32_t irqs;
|
||||
void (*handler)(void *);
|
||||
void *data;
|
||||
|
||||
/* For keeping track of how many bogus things happen in a row. */
|
||||
static int duds = 0;
|
||||
int duds_this_time = 0;
|
||||
|
||||
/* and we better have a valid bus instance. */
|
||||
KASSERT(lamebus != NULL);
|
||||
|
||||
/* Lock the softc */
|
||||
spinlock_acquire(&lamebus->ls_lock);
|
||||
|
||||
/*
|
||||
* Read the LAMEbus controller register that tells us which
|
||||
* slots are asserting an interrupt condition.
|
||||
*/
|
||||
irqs = read_ctl_register(lamebus, CTLREG_IRQS);
|
||||
|
||||
if (irqs == 0) {
|
||||
/*
|
||||
* Huh? None of them? Must be a glitch.
|
||||
*/
|
||||
kprintf("lamebus: stray interrupt on cpu %u\n",
|
||||
curcpu->c_number);
|
||||
duds++;
|
||||
duds_this_time++;
|
||||
|
||||
/*
|
||||
* We could just return now, but instead we'll
|
||||
* continue ahead. Because irqs == 0, nothing in the
|
||||
* loop will execute, and passing through it gets us
|
||||
* to the code that checks how many duds we've
|
||||
* seen. This is important, because we just might get
|
||||
* a stray interrupt that latches itself on. If that
|
||||
* happens, we're pretty much toast, but it's better
|
||||
* to panic and hopefully reset the system than to
|
||||
* loop forever printing "stray interrupt".
|
||||
*/
|
||||
}
|
||||
|
||||
/*
|
||||
* Go through the bits in the value we got back to see which
|
||||
* ones are set.
|
||||
*/
|
||||
|
||||
for (mask=1, slot=0; slot<LB_NSLOTS; mask<<=1, slot++) {
|
||||
if ((irqs & mask) == 0) {
|
||||
/* Nope. */
|
||||
continue;
|
||||
}
|
||||
|
||||
/*
|
||||
* This slot is signalling an interrupt.
|
||||
*/
|
||||
|
||||
if ((lamebus->ls_slotsinuse & mask)==0) {
|
||||
/*
|
||||
* No device driver is using this slot.
|
||||
*/
|
||||
duds++;
|
||||
duds_this_time++;
|
||||
continue;
|
||||
}
|
||||
|
||||
if (lamebus->ls_irqfuncs[slot]==NULL) {
|
||||
/*
|
||||
* The device driver hasn't installed an interrupt
|
||||
* handler.
|
||||
*/
|
||||
duds++;
|
||||
duds_this_time++;
|
||||
continue;
|
||||
}
|
||||
|
||||
/*
|
||||
* Call the interrupt handler. Release the spinlock
|
||||
* while we do so, in case other CPUs are handling
|
||||
* interrupts on other devices.
|
||||
*/
|
||||
handler = lamebus->ls_irqfuncs[slot];
|
||||
data = lamebus->ls_devdata[slot];
|
||||
spinlock_release(&lamebus->ls_lock);
|
||||
|
||||
handler(data);
|
||||
|
||||
spinlock_acquire(&lamebus->ls_lock);
|
||||
|
||||
/*
|
||||
* Reload the mask of pending IRQs - if we just called
|
||||
* hardclock, we might not have come back to this
|
||||
* context for some time, and it might have changed.
|
||||
*/
|
||||
|
||||
irqs = read_ctl_register(lamebus, CTLREG_IRQS);
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* If we get interrupts for a slot with no driver or no
|
||||
* interrupt handler, it's fairly serious. Because LAMEbus
|
||||
* uses level-triggered interrupts, if we don't shut off the
|
||||
* condition, we'll keep getting interrupted continuously and
|
||||
* the system will make no progress. But we don't know how to
|
||||
* do that if there's no driver or no interrupt handler.
|
||||
*
|
||||
* So, if we get too many dud interrupts, panic, since it's
|
||||
* better to panic and reset than to hang.
|
||||
*
|
||||
* If we get through here without seeing any duds this time,
|
||||
* the condition, whatever it was, has gone away. It might be
|
||||
* some stupid device we don't have a driver for, or it might
|
||||
* have been an electrical transient. In any case, warn and
|
||||
* clear the dud count.
|
||||
*/
|
||||
|
||||
if (duds_this_time == 0 && duds > 0) {
|
||||
kprintf("lamebus: %d dud interrupts\n", duds);
|
||||
duds = 0;
|
||||
}
|
||||
|
||||
if (duds > 10000) {
|
||||
panic("lamebus: too many (%d) dud interrupts\n", duds);
|
||||
}
|
||||
|
||||
/* Unlock the softc */
|
||||
spinlock_release(&lamebus->ls_lock);
|
||||
}
|
||||
|
||||
/*
|
||||
* Have the bus controller power the system off.
|
||||
*/
|
||||
void
|
||||
lamebus_poweroff(struct lamebus_softc *lamebus)
|
||||
{
|
||||
/*
|
||||
* Write 0 to the power register to shut the system off.
|
||||
*/
|
||||
|
||||
cpu_irqoff();
|
||||
write_ctl_register(lamebus, CTLREG_PWR, 0);
|
||||
|
||||
/* The power doesn't go off instantly... so halt the cpu. */
|
||||
cpu_halt();
|
||||
}
|
||||
|
||||
/*
|
||||
* Ask the bus controller how much memory we have.
|
||||
*/
|
||||
uint32_t
|
||||
lamebus_ramsize(void)
|
||||
{
|
||||
/*
|
||||
* Note that this has to work before bus initialization.
|
||||
* On machines where lamebus_read_register doesn't work
|
||||
* before bus initialization, this function can't be used
|
||||
* for initial RAM size lookup.
|
||||
*/
|
||||
|
||||
return read_ctl_register(NULL, CTLREG_RAMSZ);
|
||||
}
|
||||
|
||||
/*
|
||||
* Turn on or off the interprocessor interrupt line for a given CPU.
|
||||
*/
|
||||
void
|
||||
lamebus_assert_ipi(struct lamebus_softc *lamebus, struct cpu *target)
|
||||
{
|
||||
if (lamebus->ls_uniprocessor) {
|
||||
return;
|
||||
}
|
||||
write_ctlcpu_register(lamebus, target->c_hardware_number,
|
||||
CTLCPU_CIPI, 1);
|
||||
}
|
||||
|
||||
void
|
||||
lamebus_clear_ipi(struct lamebus_softc *lamebus, struct cpu *target)
|
||||
{
|
||||
if (lamebus->ls_uniprocessor) {
|
||||
return;
|
||||
}
|
||||
write_ctlcpu_register(lamebus, target->c_hardware_number,
|
||||
CTLCPU_CIPI, 0);
|
||||
}
|
||||
|
||||
/*
|
||||
* Initial setup.
|
||||
* Should be called from mainbus_bootstrap().
|
||||
*/
|
||||
struct lamebus_softc *
|
||||
lamebus_init(void)
|
||||
{
|
||||
struct lamebus_softc *lamebus;
|
||||
int i;
|
||||
|
||||
/* Allocate space for lamebus data */
|
||||
lamebus = kmalloc(sizeof(struct lamebus_softc));
|
||||
if (lamebus==NULL) {
|
||||
panic("lamebus_init: Out of memory\n");
|
||||
}
|
||||
|
||||
spinlock_init(&lamebus->ls_lock);
|
||||
|
||||
/*
|
||||
* Initialize the LAMEbus data structure.
|
||||
*/
|
||||
lamebus->ls_slotsinuse = 1 << LB_CONTROLLER_SLOT;
|
||||
|
||||
for (i=0; i<LB_NSLOTS; i++) {
|
||||
lamebus->ls_devdata[i] = NULL;
|
||||
lamebus->ls_irqfuncs[i] = NULL;
|
||||
}
|
||||
|
||||
lamebus->ls_uniprocessor = 0;
|
||||
|
||||
return lamebus;
|
||||
}
|
||||
Reference in New Issue
Block a user