Initial Spring 2016 commit.
This commit is contained in:
Geoffrey Challen
301
kern/arch/mips/thread/cpu.c
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301
kern/arch/mips/thread/cpu.c
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/*
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* Copyright (c) 2000, 2001, 2002, 2003, 2004, 2005, 2008, 2009
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* The President and Fellows of Harvard College.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE UNIVERSITY AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE UNIVERSITY OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* CPU control functions.
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*/
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#include <types.h>
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#include <lib.h>
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#include <mips/specialreg.h>
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#include <mips/trapframe.h>
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#include <platform/maxcpus.h>
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#include <cpu.h>
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#include <thread.h>
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////////////////////////////////////////////////////////////
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/*
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* Startup and exception-time stack hook.
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*
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* The MIPS lacks a good way to find the current CPU, current thread,
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* or current thread stack upon trap entry from user mode. To deal
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* with this, we store the CPU number (our number, not the hardware
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* number) in a nonessential field in the MMU, which is about the only
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* place possible, and then use that to index cpustacks[]. This gets
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* us the value to load as the stack pointer. We can then also load
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* curthread from cputhreads[] by parallel indexing.
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*
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* These arrays are also used to start up new CPUs, for roughly the
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* same reasons.
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*/
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vaddr_t cpustacks[MAXCPUS];
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vaddr_t cputhreads[MAXCPUS];
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/*
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* Do machine-dependent initialization of the cpu structure or things
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* associated with a new cpu. Note that we're not running on the new
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* cpu when this is called.
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*/
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void
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cpu_machdep_init(struct cpu *c)
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{
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vaddr_t stackpointer;
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KASSERT(c->c_number < MAXCPUS);
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if (c->c_curthread->t_stack == NULL) {
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/* boot cpu; don't need to do anything here */
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}
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else {
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/*
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* Stick the stack in cpustacks[], and thread pointer
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* in cputhreads[].
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*/
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/* stack base address */
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stackpointer = (vaddr_t) c->c_curthread->t_stack;
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/* since stacks grow down, get the top */
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stackpointer += STACK_SIZE;
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cpustacks[c->c_number] = stackpointer;
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cputhreads[c->c_number] = (vaddr_t)c->c_curthread;
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}
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}
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////////////////////////////////////////////////////////////
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/*
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* Return the type name of the currently running CPU.
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*
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* For now, assume we're running on System/161 so we can use the
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* System/161 processor-ID values.
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*/
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#define SYS161_PRID_ORIG 0x000003ff
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#define SYS161_PRID_2X 0x000000a1
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static inline
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uint32_t
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cpu_getprid(void)
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{
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uint32_t prid;
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__asm volatile("mfc0 %0,$15" : "=r" (prid));
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return prid;
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}
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static inline
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uint32_t
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cpu_getfeatures(void)
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{
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uint32_t features;
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__asm volatile(".set push;" /* save assembler mode */
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".set mips32;" /* allow mips32 instructions */
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"mfc0 %0,$15,1;" /* get cop0 reg 15 sel 1 */
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".set pop" /* restore assembler mode */
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: "=r" (features));
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return features;
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}
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static inline
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uint32_t
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cpu_getifeatures(void)
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{
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uint32_t features;
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__asm volatile(".set push;" /* save assembler mode */
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".set mips32;" /* allow mips32 instructions */
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"mfc0 %0,$15,2;" /* get cop0 reg 15 sel 2 */
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".set pop" /* restore assembler mode */
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: "=r" (features));
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return features;
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}
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void
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cpu_identify(char *buf, size_t max)
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{
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uint32_t prid;
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uint32_t features;
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prid = cpu_getprid();
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switch (prid) {
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case SYS161_PRID_ORIG:
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snprintf(buf, max, "MIPS/161 (System/161 1.x and pre-2.x)");
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break;
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case SYS161_PRID_2X:
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features = cpu_getfeatures();
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snprintf(buf, max, "MIPS/161 (System/161 2.x) features 0x%x",
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features);
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features = cpu_getifeatures();
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if (features != 0) {
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kprintf("WARNING: unknown CPU incompatible features "
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"0x%x\n", features);
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}
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break;
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default:
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snprintf(buf, max, "32-bit MIPS (unknown type, CPU ID 0x%x)",
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prid);
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break;
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}
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}
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////////////////////////////////////////////////////////////
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/*
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* Interrupt control.
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*
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* While the mips actually has on-chip interrupt priority masking, in
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* the interests of simplicity, we don't use it. Instead we use
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* coprocessor 0 register 12 (the system coprocessor "status"
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* register) bit 0, IEc, which is the global interrupt enable flag.
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* (IEc stands for interrupt-enable-current.)
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*/
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/*
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* gcc inline assembly to get at the status register.
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*
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* Pipeline hazards:
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* - there must be at least one cycle between GET_STATUS
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* and SET_STATUS;
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* - it may take up to three cycles after SET_STATUS for the
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* interrupt state to really change.
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*
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* These considerations do not (currently) apply to System/161,
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* however.
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*/
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#define GET_STATUS(x) __asm volatile("mfc0 %0,$12" : "=r" (x))
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#define SET_STATUS(x) __asm volatile("mtc0 %0,$12" :: "r" (x))
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/*
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* Interrupts on.
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*/
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void
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cpu_irqon(void)
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{
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uint32_t x;
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GET_STATUS(x);
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x |= CST_IEc;
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SET_STATUS(x);
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}
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/*
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* Interrupts off.
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*/
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void
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cpu_irqoff(void)
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{
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uint32_t x;
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GET_STATUS(x);
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x &= ~(uint32_t)CST_IEc;
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SET_STATUS(x);
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}
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/*
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* Used below.
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*/
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static
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void
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cpu_irqonoff(void)
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{
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uint32_t x, xon, xoff;
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GET_STATUS(x);
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xon = x | CST_IEc;
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xoff = x & ~(uint32_t)CST_IEc;
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SET_STATUS(xon);
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__asm volatile("nop; nop; nop; nop");
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SET_STATUS(xoff);
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}
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////////////////////////////////////////////////////////////
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/*
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* Idling.
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*/
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/*
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* gcc inline assembly for the WAIT instruction.
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*
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* mips r2k/r3k has no idle instruction at all.
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*
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* However, to avoid completely overloading the computing cluster, we
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* appropriate the mips32 WAIT instruction.
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*/
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static
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inline
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void
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wait(void)
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{
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/*
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* The WAIT instruction goes into powersave mode until an
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* interrupt is trying to occur.
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*
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* Then switch interrupts on and off again, so we actually
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* take the interrupt.
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*
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* Note that the precise behavior of this instruction in the
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* System/161 simulator is partly guesswork. This code may not
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* work on a real mips.
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*/
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__asm volatile(
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".set push;" /* save assembler mode */
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".set mips32;" /* allow MIPS32 instructions */
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".set volatile;" /* avoid unwanted optimization */
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"wait;" /* suspend until interrupted */
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".set pop" /* restore assembler mode */
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);
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}
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/*
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* Idle the processor until something happens.
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*/
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void
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cpu_idle(void)
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{
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wait();
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cpu_irqonoff();
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}
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/*
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* Halt the CPU permanently.
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*/
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void
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cpu_halt(void)
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{
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cpu_irqoff();
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while (1) {
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wait();
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}
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}
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